The present invention relates to overload protection circuitry and, more particularly, to a circuit and method for limiting the power dissipated in a semiconductor device during short circuit load conditions.
Power transistors are commonly used in circuits to provide a series conduction path between a source of operating potential and a load. These circuits are referred to as series-pass or high side driver circuits. For example, the automotive industry utilizes different types of high side driver circuits to provide a myriad of functions. A typical high side driver circuit has the two main electrodes of the transistor series connected between the positive, or high side, of the battery and the load with the transistor control electrode driven by electronic control circuitry to render the transistor conductive to source current to the load. A feature of such circuits is that the "on" resistance of the transistor is minimal in order that very little voltage is dropped thereacross. Thus, the load is effectively connected to the high side of the battery.
At least one automotive manufacturer has proposed using a power Field Effect Transistor (FET) in such a high side driver circuit. In this application the drain and source electrodes are connected between the battery and the load respectively. The gate electrode is connected to electronic control circuitry including a charge pump circuit for supplying a gate-to-source drive voltage, VGS, of sufficient magnitude to render the FET conductive during normal operation such that the "on" resistance of the device is minimal, i.e., only a few tenths of an ohm. As understood, the charge pump circuit can develop a VGS of several magnitudes greater than the battery voltage: typically 25 to 30 volts. Hence, the FET can supply eight to ten amperes of current to the load with minimal voltage drop thereacross. A typical value of VDS, the drain-to-source voltage potential of the FET under normal operating conditions is less than a hundred millivolts. Thus, the FET power dissapation is well within the safe operating conditions of the device.
A problem occurs if the load that is coupled to the source electrode of the power FET in the above described circuit should become an effective short circuit. Under this condition the voltage across the FET could approach the battery potential which, in conjunction with VGS being between 25-30 volts, can cause over 600 watts to be dissipated across the FET due to in rush currents of greater than 60 amperes flowing therethrough. Hence, the FET could be seriously damaged or even destroyed.
It is known that short circuit current flow in the FET can be limited to reduce the power dissapation therein by voltage source driving the FET gate electrode with respect to the source electrode under certain conditions. Hence, by controlling V.sub.GS of the FET in the saturated operating region the source current can be controlled. The source current then is substantially constant to a first order and is independent of V.sub.DS, the drain-to-source voltage.
However, because of present day process tolerances, it is not uncommon to find the transconductance of power FET's varying from FET to FET and process to process. Hence, it is not uncommon to discover that the short circuit current flow through the same circuitry using a different FET connected therewith can vary widely with a given VGS. This condition is very undesirable since it may be necessary to limit the short circuit current of the FET to a minimal value in order to protect the FET during short circuit load conditions.
Hence, a need exists for a circuit and method for adjusting the short current flow in a power FET connected to the circuit to a predetermined maximum value in order to limit the power dissipation therein.